1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication, and more particularly to the method of fabricating a semiconductor structure using a chemical mechanical polishing (CMP) process and a cleaning process.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
Currently, since gate height loading may induce potential risk on removal of dummy gate during replacement metal gate (RMG) stage in FinFET fabrication process, the control of gate height uniformity has been an important factor for device performance improvement. Hence, how to improve the current FinFET fabrication to resolve the aforementioned issue has become an important task in this field.